1. Field of the Invention
The present invention relates to a method of manufacturing a Schottky diode device.
2. Description of the Related Art
Schottky barrier diodes are semiconductor diodes formed by contact between a semiconductor layer and a metal layer, and have a nonlinear rectifying property. Of Schottky barrier diodes, a device is known from Published Examined Japanese Patent Application No. 59-35183, which includes a plurality of semiconductor regions formed in a semiconductor substrate, and a single metal layer contacting the semiconductor regions. Each semiconductor region forms a Schottky diode with the metal layer. Thus, the metal layer electrically connects the Schottky diodes in parallel.
More specifically, the diode device disclosed in the Japanese Publication has an N type epitaxial layer formed on a N+ silicon substrate. The surface area of the epitaxial layer is divided into a plurality of device formation regions by annular insulating layers. In each of the device formation regions, a number of P+ regions are selectively formed. A single metal layer is formed covering the surface of each device formation region, and an electrode metal is formed on the metal layer. A back electrode is formed on the back surface of the substrate.
The above-mentioned diode device is fabricated by forming an insulating layer on an entire surface of the epitaxial layer, followed by patterning a positive resist coated on the insulating layer through a photomask. The pattern of the photomask is projected on the positive resist with its size reduced, for example, to 1/5, using a stepper. The resultant resist pattern includes an annular, square isolation region-defining open pattern having a open width of about, e.g., 50 .mu.m. The annular open pattern defines therewithin a device-forming region having a size of about 3,180 .mu.m.times.3,180 .mu.m in the surface region, of the N-type epitaxial layer, having a size of 3,500 .mu.m.times.3,500 .mu.m. Within the region enclosed by the annular open pattern, a large number of individual fine openings for defining semiconductor regions having a diammeter of, e.g., 1 .mu.m are formed into a square matrix or staggered matrix at a pitch of e.g., 3 to 10 .mu.m. Another annular open pattern is provided outside the resist to define the annular insulating layer having a width of, e.g., 150 .mu.m with the first annular open pattern.
When the patterned resist thus formed is baked (post baking), the patterned resist is thermally shrunk from its peripheral portion toward its central portion due to the heat of the baking. As a result, the shape of the pattern formed in the resist is changed. For example, when the patterned resist having a size of 3,180 .mu.m.times.3,180 .mu.m is shrunk by a %, a positioning error of 3,180 (.mu.m).times.(a/100).times.31.8.times.a (.mu.m) occurs in an opening pattern of the peripheral portion of the resist. In fact, it was found that the positioning error of 0.3 .mu.m occurred at an opening having a diameter of 1 .mu.m of the peripheral portion of the resist.
More specifically, as shown in FIG. 1A, in the plane of the patterned resist after baking, the openings 5 of the peripheral portion is deviated toward the central portion with respect to the openings 3 before baking, though the position of each opening pattern 4 at the central portion of the resist is not shifted. As shown in FIG. 1B, the sectional shape of the openings 5 at the peripheral portion of the resist 1 is largely inclined toward the central portion, since the surface portion of the resist is mainly shrunk.
Referring to FIG. 1C, when anisotropy etching such as reactive ion etching (RIE) is performed to pattern the insulating layer 2 (e.g., silicon dioxide) formed on the substrate, using such a deformed patterned resist as a mask, the size L1 of the resulting openings 6 in the oxide 2 at the peripheral portion is smaller than the size L2 of the openings 6 at the central portion, since an effective area of the openings in the resist 1 at the peripheral portion is smaller.
When the patterned insulating layer 2 in which the size L2 of the openings 6 at the central portion is largely different from the size L1 of the openings 6 of the peripheral portion is used as a mask, and ion implantation is performed to form p.sup.+ -type regions in the semiconductor substrate, the resulting p.sup.+ -type regions become narrower at the peripheral portion of the device region, and, in the worst case, the p.sup.+ -type region is not formed. Thus, a Schottky barrier can not be formed with high dimensional accuracy. Therefore, as shown in FIG. 2, when a reverse bias is applied to a p-n junction between each p.sup.+ -type region 8 and an n-type epitaxial layer 9, depletion layers 10 formed around the p.sup.+ -type regions 8 at the peripheral portion of the device region are not combined, or a reverse bias of as large as, e.g., 0.5 V or more must be applied to combine the depletion layers 10. As a result, a leakage current is increased, resulting in failure to obtain a diode device having excellent electric properties.